Efficient CMOS subthreshold leakage analysis with improved stack based models in presence of parameter variations

Presented is the error that occurs while estimating subthreshold leakage power of parallel transistor stacks in CMOS gates using leakage power models when there is no consideration of the manufacturing variations, i.e. device geometry related effects in width. For the purpose, efficient support vector machine based macromodels for characterising the transistor stacks of CMOS gates are reported, considering process parameter variations impacting e.g. length, threshold voltage, oxide thickness, supply voltage, temperature and width of the transistors. The experiments show that maximum error can go up to ~15% for AOI22 and OAI22 gate under nominal values of varying parameters without considering manufacturing variations in the width.