A 0.39–0.44 THz 2x4 Amplifier-Quadrupler Array With Peak EIRP of 3–4 dBm

Author

Golcuk, Faith ; Gurbuz, Ozan Dogan ; Rebeiz, Gabriel M.

Author_Institution

Electr. & Comput. Eng. Dept., Univ. of California San Diego, La Jolla, CA, USA

Volume

61

Issue

12

fYear

2013

fDate

Dec. 2013

Firstpage

4483

Lastpage

4491

Abstract

This paper presents a CMOS amplifier-multiplier-antenna array capable of generating an EIRP of 3-4 dBm at 420 GHz. The chip is built using a 45-nm CMOS SOI process, and efficient on-chip antennas are used to extract the power out of the chip. The design is based on a 90-110 GHz distribution network with splitters and amplifiers, and a balanced quadrupler capable of delivering up > 100 μW of power at 370-430 GHz. The amplifier-multiplier concept is proven on a 2×4 array, and it can be also scaled to any N×M array using additional W-band splitters and amplifiers.

Keywords

CMOS integrated circuits; antenna arrays; silicon-on-insulator; submillimetre wave amplifiers; submillimetre wave antennas; CMOS SOI process; CMOS amplifier-multiplier-antenna array; W-band amplifiers; W-band splitters; amplifier-multiplier concept; amplifier-quadrupler array; balanced quadrupler; distribution network; frequency 0.37 THz to 0.44 THz; frequency 90 GHz to 110 GHz; on-chip antennas; peak EIRP; size 45 nm; Arrays; Gain; Harmonic analysis; Loss measurement; Power generation; Power measurement; Slot antennas; CMOS; EIRP; THz sources; frequency multiplier; mm-wave; on-chip antenna; quadrupler; slot-ring antenna;

fLanguage

English

Journal_Title

Microwave Theory and Techniques, IEEE Transactions on

Publisher

ieee

ISSN

0018-9480

Type

jour

DOI

10.1109/TMTT.2013.2287493

Filename

6668993