Title :
One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes
Author :
Lacruz, Jesus O. ; Garcia-Herrero, Francisco ; Valls, Javier ; Declercq, David
Author_Institution :
Electr. Eng. Dept., Univ. de Los Andes, Merida, Venezuela
Abstract :
A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, and propose efficient estimators to infer the second minimum value. By doing so, we greatly reduce the complexity and at the same time improve latency and throughput of the derived architectures compared to the existing implementations of EMS and Min-max decoders. This solution has been applied to various NB-LDPC codes constructed over different Galois fields and with different degree distributions showing in all cases negligible performance loss compared to the ideal EMS and Min-max algorithms. In addition, two complete decoders for OMO T-EMS and OMO T-MM were implemented for the (837,726) NB-LDPC code over GF(32) for comparison proposals. A 90 nm CMOS process was applied, achieving a throughput of 711 Mbps and 818 Mbps respectively at a clock frequency of 250 MHz, with an area of 19.02 mm2 and 16.10 mm2 after place and route. To the best knowledge of the authors, the proposed decoders have higher throughput and area-time efficiency than any other solution for high-rate NB-LDPC codes with high Galois field order.
Keywords :
CMOS integrated circuits; Galois fields; computational complexity; decoding; minimax techniques; parity check codes; trellis codes; CMOS process; GF; Galois field; NB-LDPC code; OMO T-EMS; Trellis extended min-sum; Trellis-minmax; area-time efficiency; check node processor; clock frequency; computational complexity reduction; frequency 250 MHz; latency improvement; nonbinary low density parity check code; one minimum only decoder for Trellis-EMS; size 90 nm; Approximation algorithms; Approximation methods; Computer architecture; Decoding; Estimation; Hardware; Throughput; Check node processing; NB-LDPC; OMO T-EMS; OMO T-MM; VLSI design; low-latency;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2014.2354753