Title :
A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits
Author :
Yankang Du ; Shuming Chen ; Biwei Liu
Author_Institution :
Sci. & Technol. on Parallel & Distrib. Process. Lab., Nat. Univ. of Defense Technol., Changsha, China
Abstract :
A novel constrained layout placement approach is proposed to enhance the pulse quenching effect in combinational circuits. This constrained algorithm can enlarge the number of quenching cells and shrink the distance between these cells. Simulation results illustrate that the soft error vulnerabilities are effectively reduced by adopting this novel constrained layout placement algorithm with no area penalty.
Keywords :
combinational circuits; integrated circuit layout; radiation hardening (electronics); radiation quenching; combinational circuits; constrained layout placement; pulse quenching effect; quenching cells; soft error vulnerability; Combinational circuits; Ions; Layout; Logic gates; MOSFET; Standards; Vectors; Constrained layout; multi-node charge collection; pulse quenching effect; quenching cells;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2013.2291409
