Statistical Viability Analysis for Detecting False Paths Under Delay Variation

How long does an integrated circuit take to produce its result? To answer the question, we must tackle the difficult and complex false path detection problem first. The viability analysis is one of the most sophisticated approaches to the false path detection problem. On the other side, as the technology scales down, the gate delay variation has made a significant impact on the circuit reliability. Nevertheless, so far the previous timing analyzers have invariably used the worst-case gate delay in their false path detection algorithms, missing some important false or true path timing behavior. In this paper, we propose a solid method of viability analysis under delay variation to solve the false path detection problem under delay variation, which has never been addressed by the prior works of timing analysis. In addition to the thorough theoretical results, to cope with the runtime problem in evaluating the viability for large circuits in practice, we propose an efficient viability evaluation technique that is able to soothe the complexity of the numbers of input vectors. We tested the proposed method on ISCAS benchmark circuits and carry bypass adders under delay variation, and showed its effectiveness and usefulness on the false path aware statistical timing analysis.