DocumentCode
1763318
Title
Ambipolar Independent Double Gate FET (Am-IDGFET) for the Design of Compact Logic Structures
Author
Jabeur, Kotb ; OConnor, Ian ; Le Beux, Sebastien
Author_Institution
INL, Ecole Centrale de Lyon, Ecully, France
Volume
13
Issue
6
fYear
2014
fDate
Nov. 2014
Firstpage
1063
Lastpage
1073
Abstract
Among potential candidates to replace the CMOS transistor channel, several materials such as CNTs, GNRs, and SiNW show an interesting behavior known as “Ambipolarity.” Ambipolarity, means that n- and p-type behavior can be observed in the same device. By adding a fourth terminal to control the ambipolarity, a new category of devices has seen the light under the name of Ambipolar Independent Double Gate FETs “Am-IDGFETs.” These devices are capable of operating as either n-type or p-type switches according to their back-gate bias voltage. As a result, more options are available with no counterparts in CMOS technology. Based on Am-IDGFETs, we propose a circuit design approach to achieve compact logic structures by merging every two transistors in series structure using the in-field controllability via the back-gate of ambipolar devices. The approach is demonstrated for two logic styles: with a complementary static logic design style, it demonstrates an efficiency that can improve the compactness of logic structure by a factor of 2x, while with a dynamic logic style, a gain of 30% in terms of transistors count is achieved for a variety of application scenarios. We evaluate the performances of circuits designed from this approach in a case study focused on double gate carbon nanotube FET technology. Simulations results show that, with respect to conventional CMOS-16 nm gates and for comparable power consumption, time delay and integration density can both be improved by a factor of 2x and 2.5x, respectively. The power-delay-product is improved by 30%.
Keywords
carbon nanotube field effect transistors; circuit simulation; logic design; logic gates; Am-IDGFET; CMOS transistor channel; ambipolar independent double gate FET; back-gate bias voltage; compact logic structures; complementary static logic design style; double gate carbon nanotube FET technology; dynamic logic style; power-delay-product; size 16 nm; CMOS integrated circuits; Logic gates; Materials; Merging; Periodic structures; Resistance; Transistors; Ambipolar; CNTFETs; circuit simulation; double gate; emerging technologies; logic styles;
fLanguage
English
Journal_Title
Nanotechnology, IEEE Transactions on
Publisher
ieee
ISSN
1536-125X
Type
jour
DOI
10.1109/TNANO.2014.2306071
Filename
6739070
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