On the Performance of Lateral SiGe Heterojunction Bipolar Transistors With Partially Depleted Base

This paper discusses improvements to a lateral bipolar device capable of integration into the existing CMOS process flow. With the help of simulations, we demonstrate that the emitter transit time limits the cutoff frequency of a lateral bipolar device. We show that with the introduction of a heterojunction and a partially depleted base, we can decrease the emitter transit time and increase the current gain and the cutoff frequency (f_t) of the device. For a balanced design, our simulations indicate an n-p-n device with an f_t of 812 GHz and an f_max of 1.08 THz; and a p-n-p device with an f_t of 635 GHz and an f_max of 1.15 THz. The collector current at cutoff frequency for both n-p-n and p-n-p devices is ~0.03 mA-roughly 100 times lower than commercial vertical heterojunction bipolar transistors.