• DocumentCode
    1763847
  • Title

    Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment

  • Author

    Kundu, Subhadip ; Chattopadhyay, Santanu ; Sengupta, Indranil ; Kapur, Rohit

  • Author_Institution
    Synopsys India Pvt Ltd., Bangalore, India
  • Volume
    23
  • Issue
    7
  • fYear
    2015
  • fDate
    42186
  • Firstpage
    1185
  • Lastpage
    1195
  • Abstract
    Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. Limited observability due to test response compaction negatively affects the diagnosis procedure. When multiple chains, mapped to a single compactor, fail, diagnosis becomes extremely difficult. The procedure is even more complicated because when a circuit fails the flush test, not all the patterns are applied. Only a few of the patterns are applied and the observed responses are used to diagnose the faulty chains. In this paper, we have proposed an efficient masking strategy that will be very useful for diagnosis of scan chains when multiple scan chains fail. The proposed strategy uses the redundancy in fault detection by the test patterns and masks scan chains in such a way that enough information can be provided with small increase in test pattern count. A new tester architecture that will select and apply only those patterns having enough information for diagnosis has also been proposed. Diagnostic resolution and first hit index achieved by our method are very close to their ideal values, which validate the applicability of our approach.
  • Keywords
    automatic test equipment; fault diagnosis; integrated circuit reliability; integrated circuit testing; diagnostic resolution; fault detection; first hit index; flush test; integrated circuit manufacturing process; multiple chain failure diagnosis; product cost reduction; scan chain masking strategy; single compactor; space compaction environment; test pattern count; test response compaction; tester architecture; Circuit faults; Compaction; Fault detection; Fault diagnosis; Loading; Logic gates; Very large scale integration; Automatic test equipment (ATE); masking; scan chain diagnosis; test response compaction; test response compaction.;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2014.2333691
  • Filename
    6858089