A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration

A delta-sigma (ΔΣ) phase locked loop (PLL) transmitter with an efficient modulation bandwidth calibration technique is proposed in this paper. With the proposed technique, the digital-analog mismatch between digital pre-emphasis filter and PLL is calibrated. The loop filter RC variation is tracked in the first place, and then the variation of the loop gain is calibrated by sensing the magnitude differences of the modulator between DC and ten times of the loop bandwidth. The proposed transmitter has been implemented in 0.18- μm CMOS technology for GSM/GPRS application. Measurement results show that the maximum RMS phase error of the proposed transmitter is 0.8 ^°. In addition, the measured calibration accuracies for RC and loop gain variations are 0.5% and 0.8%, respectively. By reusing the PLL locking time, 18- μs calibration time is achieved. Moreover, most parts of the calibration circuitries can be shared with the receiver chain, reducing the circuit complexity overhead.