Title :
A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration
Author :
Chien-Jian Tseng ; Chieh-Fan Lai ; Hsin-Shu Chen
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A 6-bit 1 GS/s single-channel pipeline ADC using an incomplete settling concept is presented. A background sampling-point calibration is proposed to adjust MDAC sampling point so that low gain and low bandwidth opamp can be utilized to conserve power. The prototype ADC in 65-nm CMOS process exhibits an INL of +0.76/ -0.68 LSB and a DNL of +0.72/ -0.68 LSB. Its ENOB is 5.25 bits at Nyquist input frequency with the conversion rate of 1 GS/s. It consumes 62 mW including calibration circuit power at 1 V supply and occupies an active chip area of 0.3 mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; operational amplifiers; sampling methods; CMOS process; ENOB; MDAC sampling point; Nyquist input frequency; background sampling-point calibration; calibration circuit power; incomplete settling concept; low bandwidth opamp; low gain opamp; pipeline ADC; power 62 mW; size 0.3 mm; size 65 nm; storage capacity 5.25 bit; storage capacity 6 bit; voltage 1 V; Architecture; Bandwidth; Calibration; Capacitors; Clocks; Gain; Pipelines; Background calibration; incomplete settling; pipeline analog-to-digital converter; power efficiency;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2014.2333672
