Title :
Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme
Author :
Cheng-Hao Chiang ; Li-Min Kuo ; Yu-Chen Hu ; Wen-Chun Huang ; Cheng-Ta Ko ; Kuan-Neng Chen
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bump formation can be achieved simultaneously through the bottom-up plating. Results from the analysis reveal excellent electrical characteristics and quality examination, which indicate that the proposed approach may be a good candidate for the TSV fabrication in 3-D integration.
Keywords :
copper; electroplating; seals (stoppers); three-dimensional integrated circuits; 3D integration scheme; Cu; bottom-up copper TSV plating fabrication process; bottom-up copper through-silicon via plating fabrication process; bump formation; electrical characteristics; quality examination; sealing bump approach; Current measurement; Electrical resistance measurement; Fabrication; Metals; Periodic structures; Silicon; Through-silicon vias; 3-D integration; bottom-up plating; through-silicon via (TSV);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2013.2250249
