Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface

Author

Jang-Woo Lee ; Hong-Jung Kim ; Chun-Seok Jeong ; Jae-Jin Lee ; Changsik Yoo

Author_Institution

Integrated Circuits Lab., Hanyang Univ., Seoul, South Korea

Volume

21

Issue

11

fYear

2013

fDate

Nov. 2013

Firstpage

2155

Lastpage

2159

Abstract

The interpin skew among the data and the strobe signals of a source-synchronous parallel DRAM interface is compensated by a simple delay-locked loop, which reuses the circuitry of a normal input data path. With the interpin skew compensation, the printed circuit board traces of the data and the strobe signals are allowed to have unequal length. The prototype implemented in a 0.13- μm standard CMOS process shows that the interpin skew is reduced to be less than 26 ps for a 3.2-Gb/s/pin ×8 parallel interface.

Keywords

CMOS memory circuits; DRAM chips; bit rate 3.2 Gbit/s; delay locked loop; interpin skew compensation; parallel interface; printed circuit board trace; size 0.13 mum; skew compensation technique; source synchronous parallel DRAM interface; source-synchronous parallel DRAM interface; standard CMOS process; strobe signals; Clocks; Delay; Jitter; SDRAM; Standards; Very large scale integration; CMOS; delay-locked loop (DLL); interpin skew compensation; parallel interface; synchronous DRAM (SDRAM);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2012.2227853

Filename

6389783