DocumentCode :
1764794
Title :
A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test
Author :
Scarselli, Eleonora Franchi ; Perilli, Luca ; Perugini, Luca ; Canegallo, Roberto
Author_Institution :
ARCES, Univ. of Bologna, Bologna, Italy
Volume :
62
Issue :
7
fYear :
2015
fDate :
42186
Firstpage :
1737
Lastpage :
1746
Abstract :
A receiver for capacitive coupled communication is embedded in a digital input/output pad to add the capacity for non-contact data communication, while maintaining size, ESD protection, and buffering functions unchanged, even in contact mode. The added feature allows non-contact probing of die pads and provides a reliable alternative solution to mechanical probing for electrical wafer sort testing of Systems-on-Chip (SoC) and Systems-in-Package (SiPs) because of elimination of pad damage and reduction of the force required to create stable electrical contacts between probe needles and pads. The proposed receiver detects the displacement current flowing through the capacitive channel created between the connecting probe needle and top metal pad surface when a transition in the input digital stimulus signal occurs. The receiver is designed to work up to 100 Mbit/s data rate with a power of 340 μW in a 40 nm CMOS process. The circuit trade-offs between frequency, amplitude of the step input and distance are discussed. Experimental results show that for a 5 V input voltage amplitude, the receiver allows correct data transmission at a distance up to 5 μm, which increases to 10 μm if the top aluminum layer is divided in two, using a customized I/O pad design. The feasibility of this non-contact testing approach was verified through electrical tests on two IP blocks, an LFSR, and a PLL with a scan chain, using a standard prober and a cantilever probe card designed with 19 needles of different lengths to enable both physical contact connections for power supply and non-contact capacitive coupling data communication for signals.
Keywords :
integrated circuit testing; power supply circuits; system-in-package; system-on-chip; CMOS I-O pad design; ESD protection; IP blocks; SiP; SoC; buffering functions; cantilever probe card; capacitive channel; capacitive coupled communication; circuit trade-offs; die pads; digital input-output pad; electrical contacts; embedded capacitive coupling receiver; mechanical probing; noncontact data communication; noncontact wafer probe test; physical contact connections; power 340 muW; power supply; probe needle; scan chain; size 40 nm; standard prober; systems-in-package; systems-on-chip; top metal pad surface; voltage 5 V; Couplings; Needles; Probes; Receivers; Sensors; Testing; Wireless communication; CMOS integrated circuits; Capacitive interconnect; integrated circuit testing; wireless probing;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2015.2441964
Filename :
7124542
Link To Document :
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