A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With Oversampling

In this brief, a delay-locked loop (DLL)-based burst-mode clock and data recovery (BMCDR) circuit using a 4× oversampling technique is realized for passive optical network. With the help of DLL to track the input phase, the proposed circuit can recover the burstmode data in a short acquisition time and achieve large jitter tolerance. In addition, a 2.5-GHz four-phase clock generator is embedded in the chip. Implemented with a 0.18-μm CMOS technology, experiment shows that the acquisition time can be accomplished in the time of 31 bits. Incoming 2.5-Gb/s input data of 231-1 pseudorandom binary sequence, the retimed data has a root-mean-square jitter of 8.557 ps and a peak-to-peak jitter of 32.0 ps, and the measured bit error rate is less than 10^-10. The area of the whole chip is 1.4 × 1.4 mm², where the BMCDR circuit core occupies 0.81 × 0.325 mm². The total power consumption is 130 mW from a 1.8 V supply voltage.