• DocumentCode
    1764859
  • Title

    Design of an Area-Efficient One-Dimensional Median Filter

  • Author

    Ren-Der Chen ; Pei-Yin Chen ; Chun-Hsien Yeh

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Changhua Univ. of Educ., Changhua, Taiwan
  • Volume
    60
  • Issue
    10
  • fYear
    2013
  • fDate
    Oct. 2013
  • Firstpage
    662
  • Lastpage
    666
  • Abstract
    An area-efficient 1-D median filter based on the sorting network is presented in this brief. It is a word-level filter, storing the samples in the window in descending order according to their values. When a sample enters the window, the oldest sample is removed, and the new sample is inserted in an appropriate position to preserve the sorting of samples. To increase the throughput, the deletion and insertion of samples are performed in one clock cycle, so that the median output is generated at each cycle. The experimental results have shown the improved area efficiency of our design in comparison with previous work.
  • Keywords
    integrated circuit design; median filters; signal sampling; area efficient one dimensional median filter; median output; sorting network; word level filter; Clocks; Computer architecture; Hardware; Logic gates; Microprocessors; Registers; Sorting; Median filter; one-dimensional; sorting network; word level;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2013.2277987
  • Filename
    6587493