DocumentCode
1764918
Title
3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations
Author
Jaeyong Chung ; Yonghyun Kim ; Joon-Sung Yang
Author_Institution
Dept. of Electron. Eng., Incheon Nat. Univ., Incheon, South Korea
Volume
33
Issue
12
fYear
2014
fDate
Dec. 2014
Firstpage
2005
Lastpage
2009
Abstract
Process variation models for variation tolerant designs are developed through expensive silicon characterization. This paper presents a low-cost variation characterization method that takes advantage of correlations between test items. The proposed method is based on compressed sensing (CS), a new innovative theory in signal processing and information theory, and we formulate the problem of accounting for the correlations in the form of standard CS problems, allowing us to leverage advances in CS theory. We consider wafer-level measurement results for multiple test items a 3-D signal and propose the sparsifying transform that combines the 2-D discrete cosine transform and the Karhunen-Loéve transform. Our experimental results show that the proposed method reduces the number of samples required for the same accuracy up to 2X compared to virtual probe when two test items are used.
Keywords
Karhunen-Loeve transforms; compressed sensing; correlation theory; discrete cosine transforms; integrated circuit design; integrated circuit modelling; integrated circuit testing; silicon; 2-D discrete cosine transform; 3-D probe; Karhunen-Loéve transform; compressed sensing; information theory; innovative theory; integrated circuit design; integrated circuit test; intertest-item correlation; low-cost variation characterization method; low-cost variation modeling; multiple test item; process variation model; signal processing; silicon characterization; sparsifying transform; standard CS problem; variation tolerant design; wafer-level measurement; Compressed sensing; Correlation; Dictionaries; Discrete cosine transforms; Semiconductor device modeling; Approximate Computing; Approximate computing; Compressed Sensing; Inter-testitem Correlations; VLSI Design; VLSI design; compressed sensing (CS); intertest-item correlations;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2014.2361629
Filename
6918480
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