Title :
Parallel C4 Packaging of MEMS Using Self-Alignment: Simulation and Experiments
Author :
Taprogge, Jens L. M. ; Beyeler, Felix ; Steinecker, Alexander ; Nelson, Bradley J.
Author_Institution :
Centre Suisse d´Electron. et de Microtech., Alpnach Dorf, Switzerland
Abstract :
Packaging is one of the major cost drivers for microelectromechanical systems (MEMS). Currently wire bonding is the dominant method for electrically connecting MEMS chips to the substrate. Using self-alignment, a method for packaging multiple MEMS at the same time has been developed. The presented process achieves high throughput and precise alignment at low cost. The controlled collapse chip connection (C4) process has been adapted to the specific requirements of MEMS. The combination of coarse robotics and liquid solder self-alignment guarantees precise positioning and alignment of the individual MEMS chips to the respective substrates. The new method has been implemented in a case study. In the study, force sensors were packaged. Precise angular alignment of the sensors is critical for making accurate measurements. Results of the case study are presented. The alignment motion is analyzed, compared with results in the literature, and simulated. These simulations, in combination with our experiments, indicate that the motion is dominated by solder-specific effects such as oxide removal, wetting, and flux solvent evaporation.
Keywords :
force sensors; microsensors; wetting; MEMS chips; controlled collapse chip connection process; flux solvent evaporation; force sensors; oxide removal; parallel C4 packaging; self-alignment; solder-specific effects; wetting; Bonding; Heating; Micromechanical devices; Packaging; Robots; Substrates; Surface tension; Alignment; FemtoTools; bismuth; chip-scale packaging (CSP); controlled collapse chip connection (C4); deep reactive ion etching (DRIE); direct chip attach (DCA); dynamics; flip chip; flux; force sensor; microelectromechanical systems (MEMS); microoptoelectromechanical systems (MOEMS); motion; self-alignment; silicon-on-insulator (SOI); simulation; solder paste; wafer-level packaging (WLP); wetting;
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
DOI :
10.1109/TCPMT.2013.2254489