Device Delay in GaN Transistors Under High Drain Bias Conditions

Author

Dong Seup Lee ; Laboutin, O. ; Yu Cao ; Johnson, Jerry Wayne ; Beam, Edward ; Ketterson, Andrew ; Schuette, M.L. ; Saunier, Paul ; Palacios, T.

Author_Institution

Microsyst. Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA, USA

Volume

34

Issue

7

fYear

2013

fDate

41456

Firstpage

849

Lastpage

851

Abstract

This letter studies the drain delay caused by the extension of the effective gate length in high-frequency GaN high electron mobility transistors. It is shown that the drain delay is mainly reflected in the gate-to-source capacitance (C_gs) of the device. The ratio of C_gs and transconductance (gm) is then used to accurately extract the drain delay and the result is compared with other extraction methods reported in the literature. Finally, we will use this new extraction technique to explain why short channel GaN devices show higher drain delay than longer channel transistors.

Keywords

III-V semiconductors; capacitance; gallium compounds; high electron mobility transistors; transistors; wide band gap semiconductors; drain delay; effective gate length; extraction methods; gate-to-source capacitance; high drain bias conditions; high electron mobility transistors; longer channel transistors; transconductance; Drain delay; GaN; gate extension; gate-to-source capacitance $(C_{rm gs})$; high electron mobility transistor (HEMT); short channel devices; transconductance $(g_{m})$;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2013.2262034

Filename

6530699