Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

The noise margin (NM) of an inverter is an important feature for the operation stability of the digital circuits. Owing to their simple structure, easy processes, and relatively high gain, the unipolar zero-VGS-load logic design is widely used for implementation of digital circuits in various thin-film transistor (TFT) technologies. In this paper, a simple NM model clarifying the relationship between the NM and electrical/device parameters is developed for the zero-VGS-load inverter. The model is verified by circuit simulations, and is capable of providing a useful guideline for optimal design of unipolar TFT logic circuits. Finally, the application of the derived model in a static random access memory cell design is discussed.