Investigating Reliability and Stress Mechanisms of DC and Large-Signal Stressed CMOS 65-nm RF-LDMOS by Gate Current Characterization

This paper presents reliability measurements under the dc and large-signal conditions of an LDMOS transistor integrated in the 65-nm CMOS process. The gate current was measured with a high resolution across the whole operation area with an atto-sense unit, and distinct behavior was seen in the gate current characteristics due to hot-carrier injection and Fowler-Nordheim tunneling. Several bias points were chosen for the dc stress of the transistor, and the degradation of important parameters in terms of an RF operation was studied. Furthermore, the behavior from the dc stress was compared with the large-signal stress of the device in class AB, where the output power was monitored. Results show that the operation at a supply voltage of 3.3 V shows no significant drift of transistor parameters, whereas the operation at 5 V shows an increase in the on-resistance but no changes in the quiescent current or the threshold voltage. These results are in coherence with what the dc stress at quiescent bias points for class AB showed and may imply that dc-stress measurements are sufficient in order to understand the transistor reliability during an RF operation.