DocumentCode :
1766062
Title :
Clock buffer with supply noise active compensation for reduced period jitter
Author :
Ravezzi, L.
Author_Institution :
Veloce Technol., Sunnyvale, CA, USA
Volume :
49
Issue :
18
fYear :
2013
fDate :
August 29 2013
Firstpage :
1130
Lastpage :
1131
Abstract :
A simple circuit that actively compensates supply noise and reduces period jitter in CMOS clock buffers is presented. The locally sensed supply noise modulates a current injected in the buffer output node during transitions. By injecting the current in opposite phase to the supply noise, the transient variations are counterbalanced and the jitter removed. Designed in a 28 nm CMOS technology, a chain of 16 inverters using the proposed circuit shows a period jitter up to three times smaller than that of an equally long chain of basic inverters. Conventional local supply noise filtering would require approximately 70 times the area used by the proposed circuit to achieve similar performance.
Keywords :
CMOS integrated circuits; buffer circuits; circuit noise; clocks; invertors; CMOS technology; basic inverters; clock buffers; reduced period jitter; size 28 nm; supply noise active compensation;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el.2013.1178
Filename :
6587638
Link To Document :
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