Title :
Self-Matching SRAM With Embedded OTP Cells in Nanoscale Logic CMOS Technologies
Author :
Sheng-Yen Chien ; Po-Yen Lin ; Hung-Yu Chen ; Chrong-Jung Lin ; Ya-Chin King
Author_Institution :
Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
This paper reports a new static RAM (SRAM) cell featuring its self-matching characteristic for enhanced static noise margin (SNM) in low-voltage applications. This new SRAM employs trimming devices replacing pull-down transistors to compensate mismatches. Through a blanket trimming operation enabling self-matching of the two branches, effective suppression of variability with improved SNM distribution has been successfully demonstrated in nanoscaled SRAMs.
Keywords :
CMOS logic circuits; SRAM chips; SNM distribution; SRAM cell; blanket trimming operation; embedded OTP cells; enhanced static noise margin; low-voltage applications; nanoscale logic CMOS technologies; nanoscaled SRAM; self-matching SRAM; self-matching characteristic; static RAM cell; trimming devices; Current measurement; Logic gates; SRAM cells; Storage area networks; Threshold voltage; Transistors; CMOS logic process; high- (k) metal gate; high-k metal gate; logic NVM; process variation; static RAM (SRAM); static RAM (SRAM).;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2014.2357585
