• DocumentCode
    1766119
  • Title

    Pulse width modulation schemes enabling single DC power source driven dual two-level voltage source inverter with single voltage source inverter switching

  • Author

    Srinivas, S. ; Kalaiselvi, J.

  • Author_Institution
    Dept. of Electr. Eng., Indian Inst. of Technol. Madras, Chennai, India
  • Volume
    7
  • Issue
    5
  • fYear
    2014
  • fDate
    41760
  • Firstpage
    1181
  • Lastpage
    1191
  • Abstract
    Three-level voltage space phasor can be obtained using a dual two-level voltage source inverter (VSI). Two zero sequence voltage elimination pulse width modulation (PWM) switching variants are proposed in this paper for complete elimination of zero sequence voltage (ZSV) in the dual-VSI scheme. Both the PWM variants are designed in such a way that only one inverter is switched at any instant of time; to ensure that switching power losses in the dual-VSI is limited to one inverter only at any instant of time. Analytical expressions for the dwell times of the dual-VSI are developed and presented that successfully forces the ZSV in the dual-VSI to zero; at all instants of time. As a result, both the PWMs facilitate the dual-VSI to be driven from a single DC power source only. The implementation of the proposed PWM algorithms is greatly simplified and involves just the use of instantaneous magnitudes of the reference space vector. The implementation of PWMs totally avoids the time consuming task of sector identification and do not use look up tables. The PWMs proposed in this paper are first analysed, simulated using MATLAB/SIMULINK and then verified experimentally to validate the proposed PWMs.
  • Keywords
    PWM invertors; PWM power convertors; losses; switching convertors; MATLAB-SIMULINK simulation; PWM switching; VSI; ZSV; dual two-level voltage source inverter; look up table; pulse width modulation scheme; reference space vector; single DC power source; single voltage source inverter switching; switching power loss; three-level voltage space phasor; zero sequence voltage elimination;
  • fLanguage
    English
  • Journal_Title
    Power Electronics, IET
  • Publisher
    iet
  • ISSN
    1755-4535
  • Type

    jour

  • DOI
    10.1049/iet-pel.2013.0283
  • Filename
    6809478