• DocumentCode
    1766220
  • Title

    Minimum signal modulation scheme based on a single carrier for interleaved operation of parallel phase legs in voltage source converters

  • Author

    Capella, Gabriel J. ; Gabiola, Igor ; Pou, Josep ; Zaragoza, Jordi ; Ceballos, Salvador ; Agelidis, Vassilios Georgios

  • Author_Institution
    Terrassa Ind. Electron. Group (TIEG), Tech. Univ. of Catalonia, Terrassa, Spain
  • Volume
    7
  • Issue
    5
  • fYear
    2014
  • fDate
    41760
  • Firstpage
    1305
  • Lastpage
    1312
  • Abstract
    Connecting legs in parallel is a common way to increase the output current of a power converter. Interleaving the carriers used to modulate the reference signals for each leg leads to a reduction in the output current ripple without resorting to increasing the switching frequency. A whole set of shifted carriers is required if interleaved pulse-width modulators (PWMs) are used. Implementing this by means of a digital signal processor (DSP) means that the higher the number of carriers, the higher the number of DSP timing resources required. Provided that the latter are usually limited, this could be a drawback when increasing the number of interleaved carriers. This study presents the implementation of a PWM scheme where all modulators use the same carrier offering the same results as if a set of n interleaved carriers were used. Since the proposed algorithm takes maximum benefit from the PWM units available in a DSP, a higher number of legs connected in parallel can be controlled without adding any external processing hardware. A MATLAB/Simulink model has been set up for simulation purposes. Selected experimental results obtained from a three-leg single-phase inverter are reported, confirming the effectiveness of the proposed implementation.
  • Keywords
    PWM power convertors; digital signal processing chips; DSP; DSP timing resources; Matlab-Simulink model; current ripple; digital signal processor; interleaved PWM; interleaved carrier; interleaved operation; interleaved pulse-width modulators; minimum signal modulation scheme; parallel phase legs; power converter current; reference signal modulation; shifted carriers; three-leg single-phase inverter; voltage source converters;
  • fLanguage
    English
  • Journal_Title
    Power Electronics, IET
  • Publisher
    iet
  • ISSN
    1755-4535
  • Type

    jour

  • DOI
    10.1049/iet-pel.2013.0545
  • Filename
    6809489