Analysis and Modeling of DC Current Crowding for TSV-Based 3-D Connections and Power Integrity

3-D integration using through-silicon-vias (TSVs) is emerging as one of the key technology options for continued miniaturization. However, because of increased device and current density, the reliability of the 3-D power grid and its integrity must be studied and analyzed. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. Current densities at these connections can be much higher than the expected average values, so extra care is required for accurate analysis. In prior work, TSVs are modeled as single resistors along with power grid wire segments. Such models do not capture detailed current density distribution and may miss hotspots associated with current crowding. This paper studies current crowding and its impact on 3-D power grid integrity. First, we explore the current density distribution within a TSV and its connections to the global chip power grid. Second, we implement simple TSV models to obtain current density distributions within a TSV and its local environment. These models are checked for accuracy by comparing with models simulated using finite element modeling methods. Finally, the simple TSV models are integrated with the global power grid for detailed chip-scale power analysis.