A harmonic-boosted V-band divide-by-3 frequency divider in 65nm CMOS

Author

Cruz, Hugo ; Yang-Wen Chen ; Yun-Chih Lu ; Chen, Yi-Jan Emery

Author_Institution

Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2014

fDate

24-26 March 2014

Firstpage

1

Lastpage

4

Abstract

This paper presents a low power divide-by-three injection locked frequency divider (ILFD) for the V-band implemented in 65nm CMOS technology. The divider achieves a locking range of 5.5% by using the proposed harmonic-boosting technique. The 71GHz to 75GHz locking range was measured with a maximum input power of 0dBm. The inherent MOSFET non-linearity was exploited to generate the odd-order division ratio of 3. Operating with an input frequency of 75GHz, and 1.2V supply, the divider consumes 2.04mW. The total area including pads is 0.697mm×0.664mm.

Keywords

CMOS integrated circuits; field effect MIMIC; frequency dividers; millimetre wave frequency convertors; CMOS technology; ILFD; MOSFET nonlinearity; frequency 71 GHz to 75 GHz; harmonic-boosted V-band divide-by-3 frequency divider; low power divide-by-three injection locked frequency divider; odd-order division ratio; power 2.04 mW; size 65 nm; voltage 1.2 V; CMOS integrated circuits; Frequency conversion; Frequency measurement; Frequency shift keying; Generators; Harmonic analysis; Power harmonic filters; CMOS; LC-tank; divide-by-three; harmonic-boosted; injection-locked frequency divider (ILFD); locking range;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Symposium (IWS), 2014 IEEE International

Conference_Location

X´ian

Type

conf

DOI

10.1109/IEEE-IWS.2014.6864240

Filename

6864240