Title :
Fully integrated CMOS Doherty Power Amplifier with network matching optimization for die size reduction
Author :
Carneiro, Marcos L. ; Deltimple, Nathalie ; Carvalho, Paulo H. P. ; Belot, Didier ; Kerherve, Eric
Author_Institution :
Electr. Eng. Dept., Univ. of Brasilia, Brasilia, Brazil
Abstract :
Impedance network topology optimization method is proposed for saving die area and increasing performance. The technique was applied on a fully integrated Doherty Power Amplifier design in 65nm CMOS technology. Measurement results achieve a constant 24% PAE performance over a 7 dB backoff, Pout of 23.4dBm and 15dB of gain. The optimization allowed the reduction of the number of inductors which reduced in 59% the expected die area and also increased the PAE mean performance in 5% on the high power stage and the Pout in 2dB.
Keywords :
CMOS integrated circuits; circuit optimisation; impedance matching; inductors; network topology; power amplifiers; PAE mean performance; die area; die size reduction; efficiency 24 percent; fully integrated CMOS Doherty power amplifier design; gain 15 dB; high power stage; impedance network topology optimization; inductors; network matching optimization; size 65 nm; CMOS integrated circuits; CMOS technology; Capacitors; Frequency measurement; Inductors; Optimization; Power amplifiers; CMOS integrated circuit; circuit optimization; design methodology; power amplifier;
Conference_Titel :
Microwave Conference (EuMC), 2014 44th European
Conference_Location :
Rome
DOI :
10.1109/EuMC.2014.6986674
