DocumentCode
1767226
Title
An optimised processor for FMCW radar
Author
Styles, Tim ; Wildman, Leon
Author_Institution
AptCore Ltd., Bristol, UK
fYear
2014
fDate
6-9 Oct. 2014
Firstpage
1800
Lastpage
1803
Abstract
This paper presents a digital signal processor architecture optimized for FMCW radar systems, as used in automotive, security and surveillance applications. The novel architecture is described, along with the size, power consumption and performance for key radar processing operations. Architecture features include a flexible compute unit optimized for FFT operations and a two-dimensional register file. An FPGA implementation of the processor is used to demonstrate range-Doppler processing in real-time.
Keywords
CW radar; FM radar; digital signal processing chips; field programmable gate arrays; flip-flops; radar signal processing; FFT operations; FMCW radar systems; FPGA implementation; digital signal processor architecture; flexible compute unit; key radar processing operations; power consumption; range-Doppler processing; two-dimensional register file; Computer architecture; Doppler radar; Frequency modulation; Frequency-domain analysis; Radar signal processing; Registers; Application specific integrated circuits; Digital signal processors; Radar signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference (EuMC), 2014 44th European
Conference_Location
Rome
Type
conf
DOI
10.1109/EuMC.2014.6986808
Filename
6986808
Link To Document