DocumentCode :
1768150
Title :
Challenges in bit-precise reasoning
Author :
Biere, Armin
Author_Institution :
Inst. for Formal Models & Verification, Johannes Kepler Univ., Linz, Austria
fYear :
2014
fDate :
21-24 Oct. 2014
Firstpage :
3
Lastpage :
3
Abstract :
Summary form only given. Bit-precise reasoning (BPR) precisely captures the semantics of systems down to each individual bit and thus is essential to many verification and synthesis tasks for both hardware and software systems. As an instance of Satisfiabiliy Modulo Theories (SMT), BPR is in essence about word-level decision procedures for the theory of bit-vectors. In practice, quantiers and other theory extensions, such as reasoning about arrays, are important too. In the first part of the tutorial we gave a brief overview on basic techniques for bit-precise reasoning and then covered more recent theoretical results, including complexity classification results. We discussed challenges in developping an efficient SMT solver for bit-vectors, like our award winning SMT solver Boolector, and in particular presented examples, for which current techniques fail. Finally, we reviewed the state-of-the-art in word-level model checking, and argued why it is necessary to put more effort in this direction of research.
Keywords :
Boolean functions; computational complexity; formal verification; inference mechanisms; BPR; SMT solver Boolector; bit-precise reasoning; bit-vectors; complexity classification; hardware system; reasoning about arrays; satisfiability modulo theory; software system; synthesis task; theory extension; verification task; word-level decision procedure; word-level model checking; Abstracts; Business process re-engineering; Cognition; Educational institutions; Hardware; Semantics; Tutorials;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Formal Methods in Computer-Aided Design (FMCAD), 2014
Conference_Location :
Lausanne
Type :
conf
DOI :
10.1109/FMCAD.2014.6987584
Filename :
6987584
Link To Document :
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