Improving high-level synthesis effectiveness through custom operator identification

It is increasingly common to see custom operators appear in various fields of circuit design. Custom operators that can be implemented in special hardware units make it possible to improve performance and reduce area. In this paper, we propose a design flow for identifying custom operators for high-level synthesis. Experimental results show that our approach achieves on average 19%, and up to 37% area reduction, compared to a traditional high-level synthesis. Meanwhile, the latency is reduced on average by 22%, and up to 59%. In addition, on average 74% and up to 81% code size reduction can be achieved, so synthesis runtime can be reduced.