Low-cost high-quality constant offset injection for SEIR-based ADC built-in-self-test

Linearity test is a fundamental test for ADCs in production. The stringent linearity requirement for an on-chip signal generator has made ADC built-in-self-test (BIST) solutions prohibitive in the past. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it still requires the addition of a highly stable voltage offset, which remains a daunting task. To solve this problem, this paper proposes a simple and low-power method to inject the required constant offset. It exploits the inherent capacitive sample-and-hold circuit used in various ADC architectures. It ensures the injected offset to have a very high constancy, which results in an accurate INL estimation. A 16-bit SAR ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB.