Title :
A 10-bit 100MS/s subrange SAR ADC with time-domain quantization
Author :
Ling Du ; Shuangyi Wu ; Min Jiang ; Ning Ning ; Qi Yu ; Yang Liu
Author_Institution :
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
This paper presents a 10-bit subrange successive approximation register analog-to-digital converter (SAR ADC). A 3.5-bit time-domain coarse ADC converts the analog input to the time delay of two pulse signals and a time-to-digital converter (TDC) is used to quantize the delay. The coarse ADC controls the switching of the higher 3-bit capacitors in the digital-to-analog converter (DAC). A 7-bit SAR controls the remaining capacitors. The 1-bit redundancy corrects the linearity and mismatch error of the coarse ADC. The proposed 10-bit 100MS/s ADC is designed in a 65nm CMOS technology with 1.2V power supply. Simulation results show that this design achieves 59.7dB SNDR and consumes 2.69mW. The figure-of-merit (FOM) is 34.2fJ/conversion-step.
Keywords :
CMOS digital integrated circuits; time-digital conversion; time-domain analysis; 3-bit capacitors; CMOS technology; DAC; TDC; digital-to-analog converter; figure-of-merit; mismatch error; power 2.69 mW; pulse signal; size 65 nm; subrange SAR ADC; subrange successive approximation register analog-to-digital converter; time delay; time-domain coarse ADC; time-domain quantization; time-to-digital converter; voltage 1.2 V; word length 1 bit; word length 10 bit; word length 3 bit; word length 3.5 bit; CMOS integrated circuits; Capacitors; Delays; Latches; Quantization (signal); Switches; Time-domain analysis; SAR ADC; analog-to-digital converter (ADC); subrange ADC; time-domain quantization; time-to-digital converter (TDC);
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865125
