Match enhancement in SAR ADCs by algorithmic unit capacitor assignment

This paper presents the concept of and an implementation technique for match enhancement in SAR ADCs. Conventionally the binary weighted capacitors in a SAR ADC are realized by combining unit capacitors and those unit capacitors are assigned to elements of the binary weighted array during layout. Note that an n-bit CR-SAR ADC has 2ⁿ unit capacitors whose capacitance values will follow a Gaussian distribution. This work enhances matching between binary weighted capacitors by choosing those unit capacitors closest to the median as the minimum size capacitors in the array and combining capacitors further from, but on opposite sides of, the median to give to the larger capacitors in the array. This requires rank ordering of unit capacitance values. Simulation results of an 8-Bit SAR ADC with the proposed match enhancement technique indicate that a reduction of four in the DAC area and power is attainable.