A 1-GHz direct digital frequency synthesizer in an FPGA

Author

Bergeron, Melanie ; Willson, Alan N.

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA

fYear

2014

fDate

1-5 June 2014

Firstpage

329

Lastpage

332

Abstract

The architecture and design of a high-speed quadrature direct digital frequency synthesizer (DDFS), implemented in an FPGA, is presented. The architecture is based on a novel multiplier-based angle-rotation algorithm that does not distort the magnitude of the sine and cosine outputs. This algorithm maps well into the DSP slices present in modern FPGAs. Implemented in a Xilinx Virtex-7 device, the design dissipates 54.9 mW of power at 1 GHz, a performance previously attainable only in ASIC designs.

Keywords

digital signal processing chips; direct digital synthesis; field programmable gate arrays; multiplying circuits; ASIC designs; DDFS; DSP slices; FPGA; Xilinx Virtex-7 device; cosine outputs; frequency 1 GHz; high-speed quadrature direct digital frequency synthesizer; multiplier-based angle-rotation algorithm; power 54.9 mW; sine outputs; Clocks; Digital signal processing; Field programmable gate arrays; Frequency synthesizers; Mirrors; Read only memory; Wireless communication; Direct Digital Frequency Synthesizer (DDFS); Field Programmable Gate Array (FPGA); angle rotation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865132

Filename

6865132