Title :
Additional optimizations for parallel squarer units
Author :
Son Bui ; Stine, James E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Oklahoma State Univ., Stillwater, OK, USA
Abstract :
This paper discusses modifications to algorithms to compute parallel squaring. The method described in this paper improves upon designs previously presented utilizing Boolean simplifications. The algorithms discussed in this paper significantly saves area and delay for squarers ranging from 8 bits to 32 bits. Results are shown for area, delay, and power using Virtex 5 Xilinx FPGAs.
Keywords :
digital arithmetic; Boolean simplifications; Virtex 5 Xilinx FPGAs; parallel squarer units; word length 8 bit to 32 bit; Adders; Algorithm design and analysis; Arrays; Delays; Logic gates; Noise measurement; Optimization;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865140
