Interleaved successive cancellation polar decoders

Polar codes are among the most promising error correction codes due to their ability to achieve the symmetric capacities of the binary-input discrete memoryless channels (B-DMCs). However, how to design successive cancellation (SC) decoders which can maximize the hardware utilization efficiency is still challenging due to the inherent serial nature of SC decoding algorithm. To this end, in this paper, formal design approaches for designing both the time-constrained and resource-constrained interleaved SC decoders are proposed. Compared with the state-of-the-art design, the proposed interleaved decoders can achieve more than 50% reduction in term of area-time product.