Device engineering and CMOS integration of nanoscale memristors

Our group focuses on developing better nanoscale memristor with improved performance, understanding the underlying device physics, and exploring new applications for this novel device. This paper introduces our recent work on memristor device engineering and CMOS integration. We have fabricated the smallest memristors (8 nm × 8 nm) in a crossbar array, with each of the device consumes orders of magnitude lower energy per switch event than their larger counterparts. We have demonstrated that a very thin layer of chemically produced silicon oxide can be used to make memristors that only need ~0.5 V to switch. We have also proved that with multiple oxides as switching layer, both high ON/OFF ratio and high endurance can be achieved in the same device. Finally, we successfully integrated planar memristors with CMOS substrates, implementing hybrid memristor-CMOS integrated circuit with lower switching voltages and more uniform performance.