DocumentCode
1768441
Title
Run-time SoC memory subsystem mapping of heterogeneous clients
Author
Bonatto, Alexsandro C. ; Susin, Altamiro A.
Author_Institution
Fed. Inst. of Rio Grande do Sul (IFRS), Porto Alegre, Brazil
fYear
2014
fDate
1-5 June 2014
Firstpage
578
Lastpage
581
Abstract
Systems-on-chip for multimedia applications present strict requirements for the memory subsystem regarding bandwidth and latency. Typically the CPU and several IPs are connected to a multi-client memory subsystem to access data in a shared memory channel. An arbiter manages accesses conflicts due to concurrent memory requests. In this paper it is proposed an intelligent arbitration algorithm able to classify clients at runtime, according to their access requirements. The arbiter state variables are adjusted at run-time, increasing the memory channel performance if compared to a non automated client scheduling. Simulated results showed an average latency improvement of 29.4% for a multimedia SoC.
Keywords
DRAM chips; SRAM chips; system-on-chip; CPU; DDR3 SDRAM; IPs; automated client scheduling; concurrent memory requests; heterogeneous clients; intelligent arbitration algorithm; multiclient memory subsystem; multimedia SoC; multimedia applications; run-time SoC memory subsystem mapping; shared memory channel; system-on-chip; Bandwidth; Clocks; Mathematical model; Multimedia communication; Random access memory; System-on-chip; Time factors; Adaptive System; DDR3 SDRAM; Memory Controller; Multimedia; System-on-Chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location
Melbourne VIC
Print_ISBN
978-1-4799-3431-7
Type
conf
DOI
10.1109/ISCAS.2014.6865201
Filename
6865201
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