Low-latency MAP demapper architecture for coded modulation with iterative decoding

Bit-interleaved coded modulation with iterative decoding has been widely adopted in modern wireless communication systems because of its spectral efficiency and low detection complexity. Because of the iterative decoding structure, the overall decoding latency depends on the latency of both the demapper and the channel decoder. In this work, a parallel demapper architecture is proposed for a low latency implementation. Two look-ahead techniques are proposed to further reduce the latency of the parallel architecture. Techniques exploiting the symmetry property of the labeling and the common terms of the look-ahead pre-calculation are also presented to reduce the computation complexity overhead of the proposed architecture. Implementation results show that the latency is reduced by 40% when comparing with traditional sequential demapper architecture.