DocumentCode :
1768547
Title :
A low-overhead dynamic watermarking scheme on scan design for easy authentication
Author :
Aijiao Cui ; Wei Liang ; Gang Qu
Author_Institution :
Sch. of Electron. & Inf. Eng., Harbin Inst. of Technol., Shenzhen, China
fYear :
2014
fDate :
1-5 June 2014
Firstpage :
778
Lastpage :
781
Abstract :
This paper proposes a new dynamic watermarking scheme during the Design-for-Testability (DfT) stage. The extra design constraints due to watermark are imposed on the connection styles between some scan cells. As the scan chain order is maintained, no routing overhead is caused. It thus overcomes the weakness of the watermarking schemes based on scan chain reordering, which usually incur unpredicted long routing or even congestion during physical design. Most of the performances are not compromised. Experimental results show that only negligible overhead on test power is caused while a strong authorship proof is achieved.
Keywords :
design for testability; logic design; watermarking; DfT stage; authorship proof; connection styles; design-for-testability stage; dynamic watermarking scheme; scan cells; scan chain reordering; scan design; Authentication; Educational institutions; Integrated circuits; Ports (Computers); Routing; Vectors; Watermarking; Dynamic watermarking; Low overhead; Scan design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
Type :
conf
DOI :
10.1109/ISCAS.2014.6865251
Filename :
6865251
Link To Document :
بازگشت