A novel timing-error based approach for high speed highly linear Mixing-DAC architectures

In current steering Mixing-DACs with local mixing, timing errors between the current cells is a major concern. This paper considers two types of random timing errors: delay and duty-cycle. Analysis shows that the Mixing-DAC is sensitive to delay errors, but much less sensitive to duty-cycle errors. For the required high spectral purity of future 4GHz multicarrier GSM (SFDR_RBW=85dBc), the delay spread σ(delay) should be <;36fs. Therefore, only mixing in the output stage with a single LO driver can achieve the desired linearity. The presented analysis shows that the timing of the binary cells in the segmented converter is very important, especially in a back-off scenario. Simulations confirm that accurate capacitance scaling at the high-frequency nodes of the binary current cells is crucial. A new, back-off aware segmentation trade-off is proposed, which shows the impact of the SFDRRBW and backoff requirements on the segmentation choice. The proposed methods result in an optimal Mixing-DAC architecture, implemented in 65nm CMOS, with a simulated performance of SFDRRBW=86dBc at 4GHz output frequency and -16dBFS/tone output power (10dB back-off).