Replica bias scheme for efficient power utilization in high-frequency CMOS digital circuits

Digital circuits exhibiting rail-to-rail voltage swings display large spreads in current consumption and delay over variations in process, voltage and temperature (PVT). A circuit technique is proposed to enable optimal current consumption and low delay distribution in high frequency digital circuits. A typical RF application is chosen at 5 GHz frequency, for which a divider is designed and simulated in a UMC 130nm CMOS process. With the proposed scheme, the circuit shows up to 52% reduction in current, while the relative variation in delay over PVT reduces by 70%.