Title :
Efficient list decoder architecture for polar codes
Author :
Jun Lin ; Zhiyuan Yan
Author_Institution :
Dept. of Electr. & Comput. Eng., Lehigh Univ., Bethlehem, PA, USA
Abstract :
Long polar codes achieve the capacity of binary-input discrete memoryless channels when decoded with a successive cancelation (SC) algorithm. For polar codes with short or moderate length, the decoding performance of the SC algorithm is inferior, and the cyclic redundancy check (CRC) aided successive cancelation list (SCL) algorithm achieves significantly improved performance. In this paper, we propose an efficient list decoder architecture for the CRC aided SCL algorithm. Three list decoders with list size L = 2, 4 and 8, respectively, are implemented with a 90nm CMOS technology. Compared to list decoders with L = 2 and 4 in the literature, the proposed list decoders achieve 1.42 and 2.84 times, respectively, higher hardware efficiency. The implementation with list size L = 8 demonstrates that our decoder architecture works for large list sizes.
Keywords :
CMOS integrated circuits; codecs; cyclic redundancy check codes; decoding; CMOS technology; binary-input discrete memoryless channels; cyclic redundancy check; decoder architecture; decoding performance; polar codes; size 90 nm; successive cancelation list algorithm; CMOS integrated circuits; Computer architecture; Decoding; Hardware; Indexes; Measurement; Registers;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865312
