DocumentCode :
1768741
Title :
A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing
Author :
Esmaeelzadeh, Hani ; Sharifkhani, Mohammad ; Shabany, Mahdi
Author_Institution :
Sch. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran
fYear :
2014
fDate :
1-5 June 2014
Firstpage :
1147
Lastpage :
1150
Abstract :
This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; capacitors; digital-analogue conversion; low-power electronics; CMOS technology; MDACs power dissipation; extended capacitor sharing technique; low-power pipeline ADC; noise analysis; power 4.2 mW; power analysis; power reduction; size 90 nm; word length 10 bit; CMOS integrated circuits; Capacitance; Capacitors; Noise; Pipelines; Power demand; Power dissipation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
Type :
conf
DOI :
10.1109/ISCAS.2014.6865343
Filename :
6865343
Link To Document :
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