Simulations on 130 nm technology 6T SRAM cell for Near-Threshold operation

In the field of IC technologies, there is a constant demand for energy efficiency solutions. Near-Threshold Computing (NTC) is a technique that reduces energy consumption of IC devices, but it also makes them slower. We are applying NTC to a device constructed in 130 nm CMOS technology in the purpose of designing reasonably priced low-power IC devices suitable for low performance applications. In this paper, we concentrate on how a conventional 6T SRAM cell behaves in NTC use. Memory consumes a considerable portion of area and energy of a common IC system, and therefore it is a good target for optimizing with low-energy solutions. Applying NTC to 6T SRAM is not as straightforward as merely using lower supply voltage and slower clock speed; transistor sizes inside the memory cell have to be carefully considered to make the memory reliable. Two inner NMOS transistors in 6T SRAM cell play an important role; by doubling their widths from the minimum, the reliability and the static energy consumption are improved considerably. Overall, NTC makes it possible to achieve notable savings in the energy consumption of 6T SRAM cell.