A 20-Gbps low jitter analog clock recovery circuit for ultra-wide band Radio systems

This work describes the design of high speed clock recovery circuit for UWB M-sequence based Radio systems in the analog domain to avoid the high power consumed in the analog to digital converters (ADC). The clock recovery circuit depends on two modes, the coarse tuning mode and the fine tuning mode for final locking and tracking. It is illustrated, using this method, that low jitter is achieved while maintaining high acquisition range up to the tuning range of the VCO. The method depends on using a reference M-sequence in the receiver similar to the one used in the transmitter and an analog correlation circuit. The circuits are designed using a low cost 0.25μm 95GHz f_max SiGe-HBT-BiCMOS process technology consuming an estimated power of 185mW.