Title :
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing
Author :
Nebashi, Ryusuke ; Sakimura, Noboru ; Honjo, Hiroaki ; Morioka, Ayuka ; Tsuji, Yukihide ; Ishihara, Koichi ; Tokutome, Keiichi ; Miura, Shun ; Fukami, Shunsuke ; Kinoshita, Keizo ; Hanyu, Takahiro ; Endoh, Tetsuo ; Kasai, Naoki ; Ohno, Hideo ; Sugibayashi
Author_Institution :
NEC Corp., Tsukuba, Japan
Abstract :
A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.
Keywords :
CMOS integrated circuits; MRAM devices; delay circuits; low-power electronics; signal processing; CMOS technology; MRAM technology; delay circuit; four terminal magnetic random access memory device; power efficient signal processing; size 90 nm; time domain signal processing; Accuracy; Delays; Magnetic tunneling; Neuromorphics; Resistance; Signal processing; Time-domain analysis; MRAM; delay circuit; restricted Boltzmann machine; spintronics; time-domain signal processing;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865453
