Low-power comb decimation filter for RF Sigma-Delta ADCs

An efficient multi-rate multi-stage architecture for the Comb decimation filter of Sigma-Delta ADCs is presented. Polyphase decomposition in all stages is used to reduce the operating frequency of the Comb filter. A systematic design procedure is developed in order to generate all possible combinations for the decimation factor of each stage. A third order Comb decimation filter with a total decimation factor of 16 is taken as a design example. The eight possible architectures are generated in two different CMOS processes. The performance of the generated architectures are compared in terms of power consumption, area and maximum operating frequency.