Title :
A 4 × 4 multiplier-divider-less K-best MIMO decoder up to 2.7 Gbps
Author :
Thi Hong Tran ; Ochi, Hiroshi ; Nagao, Yuhei
Author_Institution :
Grad. Sch. of Comp. Sci. & Syst. Eng., Kyushu Inst. of Technol., Iizuka, Japan
Abstract :
This paper proposes a hardware architecture of K-best-based 4 × 4 MIMO decoder that supports up to 256-QAM. The novelties such as Direct Expansion, and 2D Sorter play important roles on reducing the complexity of the decoder. In addition, the most complex operators such as divider and multiplier are eliminated in this design. As compared to the previous works, the proposed decoder achieves the highest throughput (up to 2.7 Gbps), consumes the least power (56 mW), and obtains the best hardware efficiency(15.2 Mbps/Kgate).
Keywords :
MIMO communication; decoding; error statistics; hardware architecture; multiplier divider less K-best MIMO decoder; Decoding; Modulation; Resource management; Throughput;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865480