Quantitative comparison of the power reduction techniques for samsung reconfigurable processor

With significant growth in portable multimedia devices such as smartphones, application processors (AP) play a critical role for running various multimedia applications on these devices. By considering the power constraints of such devices, we often integrate reconfigurable processors (RPs) into APs. This is because RPs offer flexibility and good performance, thereby greatly improving the power efficiency for running these multimedia applications. Like many other processors, RPs also exploit the dynamic voltage/frequency scaling (DVFS) to improve their power efficiency. Owing to the platform cost constraints, however, these RPs are often integrated to low dropout (LDO) voltage regulators (VRs) instead of switching VRs. When compared with switching VRs, LDO VRs are very inexpensive; however, they suffer from considerable power loss when they are required to deliver a low output voltage. However, many previous studies focused on analyzing the power efficiency of various DVFS techniques only with regard to the processors and did not consider the negative impact of the VR power losses on the overall power efficiency of the platform. In this work, we quantitatively compare the power efficiency of a Samsung RP (SRP) adopting the race-to-halt technique with that of the SRP exploiting the DVFS supported by LDO VRs, by considering the effect of the VR power losses. Finally, we demonstrate that using the race-to-halt technique results in high power efficiency when compared with the DVFS in a commercial processor, by considering the VR power efficiency.